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1 general description the max17600CMAX17605 devices are high-speed mosfet drivers capable of sinking /sourcing 4a peak currents. the devices have various inverting and non - inverting part options that provide greater flexibility in controlling the mosfet. the devices have internal logic circuitry that prevents shoot-through during output-state changes. the logic inputs are protected against voltage spikes up to +14v, regardless of v dd voltage. propagation delay time is minimized and matched between the dual channels. the devices have very fast switching time, combined with short propagation delays (12ns typ), making them ideal for high-frequency circuits. the devices operate from a +4v to +14v single power supply and typically consume 1ma of supply cur - rent. the max17600/max17601 have standard ttl input logic levels, while the max17603 /max17604/ MAX17605 have cmos-like high-noise margin (hnm) input logic levels. the max17600/max17603 are dual inverting input drivers, the max17601/max17604 are dual noninverting input drivers, and the max17602 / MAX17605 devices have one noninverting and one inverting input. these devices are provided with enable pins (ena, enb) for better control of driver operation. these devices are available in 8-pin (3mm x 3mm) tdfn, 8-pin (3mm x 5mm) f max ? , and 8-pin so packages and operate over the -40 n c to +125 n c temperature range. applications power mosfet switching switch-mode power supplies dc-dc converters motor control power-supply modules features s dual drivers with enable inputs s +4v to +14v single power-supply range s 4a peak sink /source current s inputs rated to +14v, regardless of v dd voltage s low 12ns propagation delay s 6ns typical rise and 5ns typical fall times with 1nf load s matched delays between channels s parallel operation of dual outputs for larger driver output current s ttl or hnm logic-level inputs with hysteresis for noise immunity s low input capacitance: 10pf (typ) s thermal shutdown protection s tdfn, max, and so package options s -40 n c to +125 n c operating temperature range typical operating circuit 19-6177; rev 1; 5/12 ordering information appears at end of data sheet. max is a registered trademark of maxim integrated products, inc. gnd outb enb outa ena v dd v dd (up to +14v) ina inb max17600 max17601 max17602 max17603 max17604 MAX17605 max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 2 v dd , ina, inb, ena, enb to gnd ........................ -0.3v to +16v outa, outb to gnd ............................................ -0.3v to +16v junction operating temperature range ......... -40 n c to +125 n c continuous power dissipation (t a = +70 n c) 8-pin tdfn (derate 23.8mw/ n c above +70 n c) ........ 1904mw 8-pin so (derate 74mw/ n c above +70 n c) ............. 588.2mw* 8-pin f max (derate 12.9mw/ n c above +70 n c) ..... 1030.9mw operating temperature range ........................ -40 n c to +125 n c junction temperature ................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +240 n c *as per jedec 51 standard. tdfn junction-to-ambient thermal resistance ( b ja ) .......... 42 n c/w junction-to-case thermal resistance ( b jc ) ................. 8 n c/w so junction-to-ambient thermal resistance ( b ja ) ........ 136 n c/w junction-to-case thermal resistance ( b jc ) ............... 38 n c/w f max junction-to-ambient thermal resistance ( b ja ) ....... 77.6 n c/w junction-to-case thermal resistance ( b jc ) ................. 5 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 12v, c l = 0f, at t a = -40 n c to +125 n c, unless otherwise noted. typical values are specified at t a = +25 n c. parameters specified at v dd = 4v apply to the ttl versions only.) (note 2) parameter symbol conditions min typ max units power supply (v dd ) v dd operating range v dd ttl versions 4 14 v hnm versions 6 14 v dd undervoltage lockout uvlo v dd rising 3 3.5 3.85 v v dd uvlo hysteresis 200 mv v dd uvlo to out_ delay v dd rising 120 f s v dd supply current idd_q not switching, v dd = 14v (note 3) 1 2 ma idd_sw v dd = 4.5v, c l = 1nf, both channels switching at 1mhz 12 18 driver output (source) (outa, outb) peak output current (sourcing) i pk-p v dd = 14v, c l = 10nf (note 3) 4 a driver output resistance pulling up (note 4) r on-p v dd = 14v, i out_ = 100ma 0.88 1.85 i v dd = 4v, i out_ = 100ma 0.91 1.95 driver output (sink) (outa, outb) peak output current (sinking) i pk-n v dd = 14v, c l = 10nf (note 3) 4 a driver output resistance pulling down (note 4) r on-n v dd = 14v, i out_ = -100ma 0.5 0.95 i v dd = 4v, i out_ = -100ma 0.52 1
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 3 electrical characteristics (continued) (v dd = 12v, c l = 0f, at t a = -40 n c to +125 n c, unless otherwise noted. typical values are specified at t a = +25 n c. parameters specified at v dd = 4v apply to the ttl versions only.) (note 2) parameter symbol conditions min typ max units logic input (ina, inb) v in_ logic-high input voltage v ih max17600/1/2 2.1 v max17603/4/5 4.25 v in_ logic-low input voltage v il max17600/1/2 0.8 v max17603/4/5 2.0 logic input hysteresis v hys max17600/1/2 0.34 v max17603/4/5 0.9 logic input leakage current i lkg v ina = v inb = 0v or v dd (max17600/1/2) -1 +0.02 +1 f a logic input bias current i bias v ina = v inb = 0v or v dd (max17603/4/5) 10 f a logic input capacitance c in (note 3) 10 pf enable (ena, enb) v en_h high level voltage max17600/1/2 2.1 v max17603/4/5 4.25 v en_l low level voltage max17600/1/2 0.8 v max17603/4/5 2.0 enable hysteresis en_ hys max17600/1/2 0.34 v max17603/4/5 0.9 enable pullup resistor to v dd r pu max17600/1/2 50 100 200 k i max17603/4/5 100 200 400 propagation delay from en_ to out_ (note 3) t pd en_ rising 7 ns en_ falling 7 switching characteristics (v dd = 14v) (note 3) out_ rise time t r c l = 1nf 6 ns c l = 4.7pf 20 c l = 10nf 40 out_ fall time t f c l = 1nf 6 ns c l = 4.7nf 16 c l = 10nf 25 turn-on delay time t d-on c l = 1nf 12 ns turn-off delay time t d-off c l = 1nf 12 ns switching characteristics (v dd = 4.5v) (note 3) out_ rise time t r c l = 1nf 5 ns c l = 4.7pf 15 c l = 10nf 28 out_ fall time t f c l = 1nf 5 ns c l = 4.7nf 10 c l = 10nf 18
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 4 electrical characteristics (continued) (v dd = 12v, c l = 0f, at t a = -40 n c to +125 n c, unless otherwise noted. typical values are specified at t a = +25 n c. parameters specified at v dd = 4v apply to the ttl versions only.) (note 2) typical operating characteristics (c l = 1nf, t a = +25 n c, unless otherwise noted.) note 2: all devices are production tested at t a = +25 n c. limits over temperature are guaranteed by design. note 3: design guaranteed by bench characterization. limits are not production tested . note 4: for soic package options, these are only typ parameters. parameter symbol conditions min typ max units turn-on delay time t d-on c l = 1nf 12 ns turn-off delay time t d-off c l = 1nf 12 ns matching characteristics (note 3) matching propagation delays between channel a and channel b v dd = 14v, c l = 10nf 8 ns rise time vs. supply voltage (c out_ = 1nf) supply voltage, v dd (v) rise time (ns) 12 10 6 8 2.5 3.0 3.5 4.0 5.0 4.5 5.5 6.0 2.0 41 4 max17600 toc01 t a = +125c t a = +25c t a = +85c t a = 0c t a = -40c fall time vs. supply voltage (c out_ = 1nf) supply voltage, v dd (v) fall time (ns) 12 10 6 8 2.5 3.0 3.5 4.0 4.5 5.0 1.5 2.0 41 4 max17600 toc02 t a = +125c t a = +25c t a = +85c t a = 0c t a = -40c propagation delay time (low to high) vs. supply voltage (c out_ = 1nf) max17600 toc03 supply voltage, v dd (v) propagation delay time (ns) 12 10 8 6 10 12 14 16 18 8 41 4 t a = +25c t a = +85c t a = 0c t a = -40c t a = +125c propagation delay time (high to low) vs. supply voltage (c out_ = 1nf) max17600 toc04 supply voltage, v dd (v) propagation delay time (ns) 12 10 8 6 10 12 14 16 18 8 41 4 t a = +25c t a = +85c t a = 0c t a = -40c t a = +125c supply current vs. supply voltage (c out_ = 0nf) supply voltage, v dd (v) supply current (ma) 12 10 8 6 1.0 1.5 2.0 2.5 3.0 500khz 0.5 41 4 max17600 toc05 1mhz 100khz no switching supply currrent vs. load capacitance (v dd = 12v, c outb = 0nf) max17600 toc06 load capacitance (nf) supply current (ma) 9 8 6 7 2 3 4 5 1 10 20 30 40 50 60 70 80 90 100 110 120 130 140 0 01 0 1mhz 500khz 100khz no switching
5 typical operating characteristics (continued) (c l = 1nf, t a = +25 n c, unless otherwise noted.) logic input voltage vs. output voltage (max17601) (v dd = +4v, c outa = 10nf) max17600 toc13 20ns/div ina 2v/div outa 2v/div logic input voltage vs. output voltage (max17601) (v dd = +4v, c outa = 4.7nf) max17600 toc10 20ns/div ina 2v/div outa 2v/div supply current vs. temperature (v dd = 12v, c out_ = 0nf) ambient temperature (c) supply current (ma) 100 80 60 40 20 0 -20 1.0 1.5 2.0 2.5 3.0 3.5 0.5 -40 120 max17600 toc07 1mhz 500khz 100khz no switching logic input voltage vs. output voltage (max17601) (v dd = +14v, c outa = 4.7nf) max17600 toc14 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17601) (v dd = +4v, c outa = 10nf) max17600 toc11 20ns/div ina 2v/div outa 2v/div input threshold voltage vs. supply voltage (c out_ = 0nf) supply voltage, v dd (v) input threshold voltage (v) 12 10 6 8 0.5 1.0 1.5 2.0 2.5 3.0 0 41 4 max17600 toc08 rising falling logic input voltage vs. output voltage (max17601) (v dd = +14v, c outa = 10nf) max17600 toc15 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17601) (v dd = +4v, c outa = 4.7nf) max17600 toc12 20ns/div ina 2v/div outa 2v/div supply current vs. logic input voltage (v dd = 12v, c out_ = 0nf) max17600 toc09 logic input voltage (v) supply current (ma) 13 12 11 10 9 8 7 6 5 4 3 2 1 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.6 01 4 rising falling max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers
6 typical operating characteristics (continued) (c l = 1nf, t a = +25 n c, unless otherwise noted.) logic input voltage vs. output voltage (max17601) (v dd = +14v, c outa = 4.7nf) max17600 toc16 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17601) (v dd = +14v, c outa = 10nf) max17600 toc17 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17604) (v dd = +14v, c outa = 4.7nf) max17600 toc18 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17604) (v dd = +14v, c outa = 10nf) max17600 toc19 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17604) (v dd = +14v, c outa = 4.7nf) max17600 toc20 20ns/div ina 5v/div outa 5v/div logic input voltage vs. output voltage (max17604) (v dd = +14v, c outa = 10nf) max17600 toc21 20ns/div ina 5v/div outa 5v/div logic output vs. enable (v dd = +14v, c outa = 0nf) max17600 toc22 4s/div ina 5v/div v dd 5v/div ena 5v/div outa 10v/div max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 7 pin description pin configurations pin name function 1 ena enable input for driver a. internally pulled to v dd through a 100k i resistor. leave unconnected for always-on operation. connect to gnd for disabling the corresponding channel. 2 ina logic input for channel a 3 gnd ground 4 inb logic input for channel b 5 outb channel b driver output. sources and sinks current for channel b to turn the external mosfet at outb on or off. 6 v dd power-supply input. bypass to gnd with one or more low-esr 0.1 f f ceramic capacitors. 7 outa channel a driver output. sources and sinks current for channel a to turn the external mosfet at outa on or off. 8 enb enable input for driver b. internally pulled to v dd through a 100k i resistor. leave unconnected for always-on operation. connect to gnd for disabling the corresponding channel. ep exposed pad (tdfn only). internally connected to gnd. do not use the ep as the only ground connection. ena + ina gnd 1 2 3 4 8 7 6 5 inb enb outa v dd outb so top view max17600 max17601 max17602 max17603 max17604 MAX17605 13 4 + 86 5 enb v dd outb 2 7 outa ena gnd inb ina tdfn top view max17600 max17601 max17602 max17603 max17604 MAX17605 top view 1 2 3 4 8 7 6 5 enb outa v dd outb inb gnd ina ena max + max17600 max17601 max17602 max17603 max17604 MAX17605
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 8 figure 1. timing diagram for the max17601/max17604 figure 2. timing diagram for the max17602/MAX17605 functional diagram outb v dd outa inb enb ena ina gnd gnd predriver v l = 5v v dd - 5v v dd - 5v v l = 5v predriver in logic level shift dow n in logic level shift up bg + uvlo + tshdn bbm predriver predriver in logic level shift up in logic level shift dow n channel a channel b bg + uvlo + tshdn bbm 10% 90% v il v ih inb outb 10% 90% v il v ih ina outa t f t d-off t r t d-on t f t d-off t r t d-on 10% 10% 90% 90% v il v il v ih v ih t r t f ina outa ina outb t d-on t f t d-off t d-off t r t d-on
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 9 detailed description the max17600CMAX17605 are high-speed mosfet drivers capable of sinking/sourcing 4a peak currents. the devices have various inverting and noninverting part options that provide greater flexibility in controlling the mosfet. the devices have internal logic circuitry that prevents shoot-through during output-state changes. the logic inputs are protected against voltage spikes up to +16v, regardless of v dd voltage. propagation delay time is minimized and matched between the dual channels. the devices have very fast switching time, combined with short propagation delays (12ns typ), making them ideal for high-frequency circuits. the devices operate from a +4v to +14v single power supply and typically consume 1ma of supply current. the max17600/max17601/max17602 have standard ttl input logic levels, while the max17603/max17604/ MAX17605 have cmos-like high-noise margin (hnm) input logic levels. the max17600/max17603 are dual inverting input drivers, the max17601/max17604 are dual noninverting input drivers, and the max17602/ MAX17605 have one noninverting and one inverting input. these devices are provided with enable pins (ena and enb) for better control of driver operation. logic inputs the max17600/max17601/max17602 have standard ttl input logic levels, while the max17603/max17604 / MAX17605 have cmos-like hnm input logic levels (see the electrical characteristics table). table 1 gives the truth table for various part options. figure 3. timing diagram for the max17600/max17603 l = logic-low, h = logic-high. figure 4. test circuit for the timing diagrams table 1. truth table enable inputs logic inputs dual noninverting driver dual inverting driver one inverting and one noninverting driver ena enb ina inb outa outb outa outb outa outb h h h h h h l l l h h h h l h l l h l l h h l h l h h l h h h h l l l l h h h l l l x x l l l l l l 10% 90% v il v ih t r t f ina outa t d-on t d-off 10% 90% v il v ih t r t f inb outb t d-on t d-off max17600 max17601 max17602 max17603 max17604 MAX17605 ena ina gnd c outb c outa inb enb outa v dd v dd outb
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 10 undervoltage lockout (uvlo) when v dd is below the uvlo threshold, the output stage n-channel device is on and the p-channel is off, independent of the state of the inputs. this holds the outputs low. the uvlo is typically 3.6v with 200mv typical hysteresis to avoid chattering. a typical falling delay of 2 f s makes the uvlo immune to narrow negative transients in noisy environments. driver outputs the devices feature 4a peak sourcing/sinking capa - bilities to provide fast rise and fall times of the mosfet gate. add a resistor in series with out_ to slow the cor - responding rise/fall time of the mosfet gate. applications information supply bypassing, device grounding, and placement ample supply bypassing and device grounding are extremely important because when large external capacitive loads are driven, the peak current at the v dd pin can approach 4a, while at the gnd pin, the peak current can approach 4a. v dd drops and ground shifts are forms of negative feedback for inverters and, if excessive, can cause multiple switching when the inverting input is used and the input slew rate is low. the device driving the input should be referenced to the devic - es gnd pin, especially when the inverting input is used. ground shifts due to insufficient device grounding can disturb other circuits sharing the same ac ground return path. any series inductance in the v dd , out_, and/or gnd paths can cause oscillations due to the very high di/dt that results when the devices are switched with any capacitive load. a 2.2 f f or larger value ceramic capacitor is recommended, bypassing v dd to gnd and placed as close as possible to the pins. when driving very large loads (e.g., 10nf) at minimum rise time, 10 f f or more of parallel storage capacitance is recommended. a ground plane is highly recommended to minimize ground return resistance and series inductance. care should be taken to place the devices as close as possible to the external mosfet being driven to further minimize board inductance and ac path resistance. power dissipation power dissipation of the devices consists of three components, caused by the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). the sum of these components must be kept below the maximum power-dissipation limit. the quiescent current is 1ma typical. the current required to charge and discharge the internal nodes is frequency dependent (see the typical operating characteristics ). the devices power dissipation when driving a ground referenced resistive load is: p = d x r on (max) x i load 2 per channel where d is the fraction of the period the devices output pulls high, r on (max) is the maximum pullup on-resist - ance of the device with the output high, and i load is the output load current of the devices. for capacitive loads, the power dissipation is: p = c load x (v dd ) 2 x freq per channel where c load is the capacitive load, v dd is the supply voltage, and freq is the switching frequency. layout information the devices mosfet drivers source and sink large currents to create very fast rise and fall edges at the gate of the switching mosfet. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. the following pcb layout guidelines are recommended when designing with the devices: ? place at least one 2.2 f f decoupling ceramic capacitor from v dd to gnd as close as possible to the ic. at least one storage capacitor of 10 f f (min) should be located on the pcb with a low-resistance path to the v dd pin of the devices. there are two ac current loops formed between the ic and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from out_ of the devices to the mosfet gate to the mosfet source and to gnd of the devices. when the gate of the mosfet is being pulled high, the active current loop is from out_ of the devices to the mosfet gate to the mosfet source to the gnd terminal of the decoupling capacitor to the v dd terminal of the decoupling capacitor and to the v dd terminal of the devices. while the charging current loop is important, the discharging current loop is also critical. it is important to minimize the physical distance and the impedance in these ac current paths. ? in a multilayer pcb, the component surface layer surrounding the devices should consist of a ground plane containing the discharging and charging current loops.
max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers 11 ordering information/selector guide note: all devices are specified over the -40c to +125c temperature range. optional 8-pin 2mm x 3mm tdfn package is available. contact your maxim sales representative for more information. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos part pin-package configuration logic levels top mark max17600 ata+ 8 tdfn-ep* (3mm x 3mm) dual/inverting ttl +boj max17600asa+ 8 so dual/inverting ttl + max17600aua+ 8 f max-ep* dual/inverting ttl +aaci max17601 ata+ 8 tdfn-ep* (3mm x 3mm) dual/noninverting ttl +bok max17601asa+ 8 so dual/noninverting ttl + max17601aua+ 8 f max-ep* dual/noninverting ttl +aacj max17602 ata+ 8 tdfn-ep* (3mm x 3mm) inverting/noninverting ttl +bol max17602asa+ 8 so inverting/noninverting ttl + max17602aua+ 8 f max-ep* inverting/noninverting ttl +aack max17603 ata+ 8 tdfn-ep* (3mm x 3mm) dual/inverting hnm +bom max17603asa+ 8 so dual/inverting hnm + max17603aua+ 8 f max-ep* dual/inverting hnm +aacl max17604 ata+ 8 tdfn-ep* (3mm x 3mm) dual/noninverting hnm +bon max17604asa+ 8 so dual/noninverting hnm + max17604aua+ 8 f max-ep* dual/noninverting hnm +aacm MAX17605 ata+ 8 tdfn-ep* (3mm x 3mm) inverting/noninverting hnm +boo MAX17605asa+ 8 so inverting/noninverting hnm + MAX17605aua+ 8 f max-ep* inverting/noninverting hnm +aacn package type package code outline no. land pattern no. 8 tdfn-ep t833+2 21-0137 90-0059 8 so s8+2 21-0041 90-0096 8 f max u8e+2 21-0107 90-0145
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles drive, san jose, ca 95134 408-601-1000 12 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/12 initial release 1 5/12 added the max17600 1C12 max17600CMAX17605 4a sink /source current, 12ns, dual mosfet drivers

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